This application relies for priority upon Korean Patent Application No. 1999-55214, filed on Dec. 6, 1999, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to memory devices and, more particularly, to a nonvolatile semiconductor memory device with an erase algorithm to electrically erasable and programmable read only memory (EEPROM) cells.
FIG. 1 is a cross-sectional view of an EEPROM cell in the prior art. The EEPROM cell has source and drain regions 2 and 3, a floating gate 4, and a control gate 5. The source and drain regions 2 and 3 are formed in a P-type semiconductor substrate (or bulk) 1. The floating gate 4 is formed on a channel region with an insulating layer having a thickness of about 100 xc3x85 interposed therebetween. The channel region is formed between the source and drain regions 2 and 3. The control gate 5 is formed on the floating gate with another insulating layer interposed therebetween.
As a non-volatile semiconductor memory device, a NOR-type flash memory device includes an array of sectors for storing information. Each of the sectors has EEPROM cells in which rows (e.g., wordlines) and columns (e.g., bitlines) are arranged in a matrix type arrangement. At each sector as an erase unit, an erase operation of the NOR-type flash memory device is carried out to erase all EEPROM cells in one sector at the same time. Various erase methods related with a flash memory device are disclosed in U.S. Pat. Nos. 5,781,477, 5,132,935, 5,220,533, 5,513,193, and 5,805,501.
All EEPROM cells, which are provided to a selected cell of a NOR-type flash memory device, are erased through a series of program, erase, and over-erase cure operations, as shown in FIG. 2. During the programming operation, voltages Vs and Vb, of 0V, are applied to a source and a bulk, respectively, a gate voltage Vg of about 10V is applied to a control gate, and 5V voltage suitable for creating a hot electron is applied to a drain. Accordingly, each of EEPROM cells is programmed. Upon the bias condition, sufficient amount of negative charges are accumulated in a floating gate of each of the EEPROM, so that the floating gate has a negative potential. The programmed EEPROM cell is called an xe2x80x9cOFF cellxe2x80x9d, and has a threshold voltage which exists within a target threshold voltage range (e.g., about 6V-8.5V) corresponding to the OFF cell.
Then the erasing operation takes place. All the EEPROM cells in the selected cell are erased at the same time by an F-N (Fowler-Nordheim) tunneling scheme. Upon the F-N tunneling scheme, about a gate voltage Vg of xe2x88x9210V is applied to a control gate of each cell, and a voltage Vb of 5V suitable for generating the F-N tunneling is applied to a semiconductor substrate. In this case, a source and a drain are situated in a floating state. Such an erase scheme is called a negative gated bulk erase (NGBE) operation. During the NGBE operation, a strong electric field of about 6-7MV/cm is established between the control gate and the semiconductor substrate, so that the F-N tunneling is induced. Thus, the charges accumulated in the floating gate move from the floating gate into the substrate (or bulk) through a thin insulating layer of about 100 xc3x85. The erased EEPROM cell is called an xe2x80x9cON cellxe2x80x9d, and has a threshold voltage which exists within a target threshold voltage range (e.g., about 0.5V-2.5V) corresponding to the ON cell.
Erasure may result in over-erasure. Over-erasure is cured in the prior art as follows.
After the NGBE operation, it is checked whether all the EEPROM cells in a sector exist within a target threshold voltage range (e.g., 0.5V-2.5V) corresponding to an ON cell. After simultaneously erasing all the EEPROM cells of the sector, an EEPROM cell having a threshold voltage of 0.5V or less is created. Conventionally, such an EEPROM cell is called xe2x80x9cover-erased cellxe2x80x9d, which can be erased by an over-erase curing operation (or erase repair operation). As a result, a threshold voltage of the over-erased EEPROM cell can be distributed within a target threshold voltage range corresponding to an ON state.
In the over-erase curing operation, a source of an over-erased EEPROM cell and a semiconductor substrate are grounded. A voltage Vg of about 3V-5V is applied to a control gate. And, a voltage Vd about 5V is applied to a drain for a predetermined time. Upon such a bias condition, negative charges, which are less than those of a program operation in amount, are accumulated in a floating gate. Thus, the foregoing over-erase curing operation is carried out to move the threshold voltage of the over-erased cell within the target threshold voltage range. Voltages Vg, Vd, Vs, Vb, which are applied to the over-erased EEPROM cell during the over-erased cure operation, are called xe2x80x9csoft-program voltagesxe2x80x9d.
In the foregoing erase method, as shown in FIG. 2, there are over-cured (or over-programmed) EEPROM cells, which remain over-cured even after the over-erased cure operation. These cells can be erased by carrying sequential steps of program, erase, and over-erase curing operation again.
When a read operation is carried out, the over-cured EEPROM cell scarcely has an ON cell sensing margin left. In the worst case, the over-cured EEPROM cell can even be sensed as an OFF cell. One of the causes to generate such a phenomenon is too wide a target threshold voltage range corresponding to an ON cell. Namely, the phenomenon results from diversity of program and erase characteristics (e.g., program and erase speed) of each EEPROM cell. More specifically, this will be described as follows.
As an integration level of a flash memory device increases, a size (especially, channel width) of each EEPROM cell has been reduced. This leads to reduction of charges stored in a floating gate. Accordingly, even though change in a manufacturing process is little, a difference of program and erase characteristics becomes great. And, as an EEPROM cell size becomes small, the process is variously changed to diversify program and erase characteristics of the EEPROM cell. Upon the identical bias condition, it is known that such a phenomenon is caused by disparity between capacitance elements of each cell, change in thickness of a tunnel oxide layer, doping concentration of a floating gate, and so on.
In FIG. 3, the symbols Co, Cs, and Cc denote capacitance between a wordline and a floating gate, capacitance between a floating gate and a source, and a channel capacitance, respectively.
Out of the capacitance elements in each cell, a drain coupling ratio (DCR) has a great influence on the program and erase characteristics. As an integration level of a memory device increases (i.e., an EEPROM cell size becomes small), the DCR becomes greater. Therefore, the program and erase characteristics are more diversified (a threshold voltage range corresponding to an ON cell becomes wider). As known by the following equation, the DCR is decided by a ratio of capacitance (Cb) between a bitline node of a cell and a floating gate to total capacitance (Co+Cs+Cb+Cc), as represented hereinbelow.
DCR=Cb/Co+Cs+Cb+Cc
For example, a voltage Vf induced to a floating gate of an unselected EEPROM cell coupled to the same column as one selected cell is decided by a drain coupling ratio DCRxc3x97Vd. If the DCR is 0.1 and a bitline voltage Vd is 5V, a voltage about 0.5V is induced to the floating gate of the unselected cell. If the threshold voltage of the unselected cell is 0.5V, an unselected EEPROM cell is conducted, even though a voltage of 0V is applied to a control gate of the unselected cell. Thus, a current about 1 xcexcA flows through the unselected EEPROM cell. During a program operation, a voltage on a bitline of a selected cell becomes low by the drain coupling effect of a plurality of unselected cells that are coupled to the selected column. This prevents the selected cell from being programmed. Similarly to the program operation, a read operation cannot be carried out because a current flows through an unselected cell by the above-mentioned drain coupling effect.
And, a voltage of a flash memory device becomes low, widening a threshold voltage range of an ON cell. A maximum value (upper limited value) of the threshold voltage range becomes small because a wordline voltage (gate voltage) becomes low according to trend toward a low voltage. This causes increase in over-erased EEPROM cells. Namely, a target threshold voltage range corresponding to an ON cell is widened. And, a minimum value of the threshold voltage range corresponding to the ON cell is decided by considering the above-mentioned drain coupling effect.
As the threshold voltage range corresponding to the ON cell is widened, the number of the over-erased EEPROM cells increases. Using specific soft-program voltages Vd=5V, Vg=3V-5V, Vb=0V, and Vs=0V (these voltage are decided with reference to typical cells), a conventional cure operation for curing the over-erased cells is carried out. However, since the conventional cure operation does not consider program characteristics (e.g., program speed) of the EEPROM cells, over-erased EEROM cells can be created, as shown in FIG. 2. Soft-program voltages such as a gate voltage (wordline voltage) or a drain voltage (bitline voltage) of lower levels are applied to over-erased EEPROM cells during the over-erased cure operation, preventing over-erased cure of EEPROM cells. In this case, since a time taken for the over-erased cure operation increases, the total time also increases.
It is an object of the present invention to provide a non-volatile semiconductor memory device, which is able to cure its over-erased cells without over-curing them.
It is another object of the invention to provide a method for curing overerased cells without over curing them.
The invention provides a flash memory device with a sector of an electrically erasable and programmable read only memory (EEPROM) cells that are arranged at intersections of rows and columns. The device includes a row selection circuit for selecting one of the rows in response to a row address, a column selection circuit for selecting a part of the columns in response to a column address, a row address generator for generating the row address, and a column address generator for generating the column address.
The device also includes a high voltage generator for generating a wordline voltage and a bitline voltage which are to be applied to the selected EEPROM cell, and a control circuit for checking whether at least one of the selected EEPROM cells is over-erased during an over-erase cure operation.
A loop counter executes count up operations in the row address generator and the column address generator to step through all the cells. A pass/fail check and control logic then checks whether the memory cells are over-erased. If it is determined that one of the selected EEPROM cells is over-erased, the control circuit controls a step counter, to cause the high voltage generator to iteratively increase one of the bitline and wordline voltages. The gradual increase cures the over erasure, but without overcuring it.
According to an aspect of the present invention, there is an erase algorithm of a flash memory device. In the erase algorithm, all memory cells of the sector are erased at the same time. When one of a group of the erased memory cells is over-erased, soft-program voltages are applied to the over-erased memory cell such that the over-erased memory cell is soft-programmed. After incrementally boosting up one of the soft-program voltages, the operations of checking, and soft-programming are iteratively carried out until a threshold voltage of the over-erased memory cell moves within a target threshold voltage range of the erased memory cell.
Depending on such an erase algorithm, over-erased cells can be cured according to program characteristics without giving rise to an over-curing phenomenon.